Last Updated Dec.18, 2000

Trio Adiono, Tsuyoshi Isshiki, Kazuhito Ito, Dongju Li, Chawalit Honsawek, and Hiroaki Kunieda ``New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec'', IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, To be published in 2001

Chawalit Honsawek, Kazuhito Ito, Tomohiko Ohtsuka, Trio Adiono, Dongju Li, Tsuyoshi Isshiki, and Hiroaki KunieDa, "System-MSPA Design of H.263+ Video Encoder/Decoder LSI for Videotelephony Applications", IEICE Transactions fundamentals, Special Section on VLSI Design and CAD Algorithms, to be published in November 2001

D.J. Li, L. Jiang, T. Isshiki, and H. Kunieda, ``New VLSI Array Processor Design for Image Window Operationsg'', IEEE Transactions on Circuits and Systems, II: Analog and Digital Signal Processing, Vol. 46, No. 5, pp. 635-639, May, 1999.

Dongju Li, Li, Jiang, and Hiroaki Kunieda, ``Design Optimization of VLSI Array Processor Architecture for Window Image Processing'', The Institute of Electronics, Information and Communication Engineers Transactions(IEICE TRANS) on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on Digital Signal Processing, Vol. E82-A, No. 8, pp. 1475-1484, August, 1999.

Li, Jiang, Dongju Li, Shintaro Haba, Chawalit, and Hiroaki Kunieda, "Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm'' The Institute of Electronics, Information and Communication Engineers Transactions (IEICE TRANS) Fundamentals, Special Section on Digital Signal Processing, Vol.E79-A, No.8, Pp. 1667-1675, August, 1998.

Dongju Li and Hiroaki Kunieda, "Memory Sharing Processor Array(MSPA) Architecture" The Institute of Electronics, Information and Communication Engineers Transactions(IEICE TRANS) on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on VLSI Design and CAD Algorithms Vol. E79-A, No. 12 Pp.2086-2096, Dec. 1996.

Dongju Li and Hiroaki Kunieda, "Automatic Synthesis of a Serial Input Multiprocessor Array" The Institute of Electronics, Information and Communication Engineers Transactions(IEICE TRANS) on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on VLSI Design and CAD Algorithms}, Vol. E79-A, No. 12 Pp. 2097-2105, Dec. 1996 .

International Conference

Trio Adiono, Tsuyoshi Isshiki, Kazuhito Ito, Tomohiko Ohtsuka, Dongju Li, Chawalit Honsawek, and Hiroaki Kunieda ``Face Focus Coding Under H.263+ Video Coding Standard'', APCCAS'2000 Tianjin, China, Dec.4-6,2000.

Chawalit Honsawek, Kazuhito Ito, Tomohiko Ohtsuka, Tsuyoshi Isshiki, Dongju Li, Trio Adiono, and Hiroaki Kunieda "System-MSPA design of H.263+ Video Encoder LSI for Face Focused Videotele phony" APCCAS'2000 Tianjin, China, Dec.4-6,2000.

Mohamed Mostafa, Dongju LI, and Hiroaki Kunieda, ``Minutia Ridge Shape Algorithm For Fast on Line Fingerprint identification System'', ISPACS'2000 Hawaii, U.S.A, Nov.5-7,2000.

Dongju Li, Trio Adiono, Chawalit Honsawek, and Hiroaki, ``Multimedia LSI Design Based on Window-MSPA Architecture'', ISPACS'99 Thailand, Pucket, Dec.8-10,1999 (Invited Paper).

Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, and Hiroaki Kunieda "Motion Estimator LSI for MPEG2 High level Standard", Proceedings of Asia and Sourth Pacific design Automation Conference (ASP-DAC), January 18-21, 1999.

Dongju Li, Li Jiang, Tsuyoshi Isshiki, and Hiroaki, ``Array Architecture and Design for Image Window Operation Processing ASICs'', Proceedings of IEEE 1998 International Symposium on Circuit and Systems, Monterey, CA, U.S.A. June 1-3, 1998.

Li Jiang, Dongju Li, Shintaro Haba, Chawalit, and Hiroaki Kunieda "Towards One Chip HDTV MPEG2 Encoder LSI", Proceedings of IEEE Custom Intergrated Circuits Conference, pp173-176, San Francisco, U.S.A. May, 1998.

Dongju Li and Hiroaki Kunieda, ``New Array Processor Architecture for MPEG2 Motion Estimation'', Proceedings of 7th International Symposium on IC Technology, Systems & Applicatons, pp632-635, Singapore, September, 1997.

Dongju Li and Hiroaki,``Programmable Design for Memory Sharing Processor Array (MSPA)'', Proceedings of IEEE 1997 International Symposium on Circuit and Systems, Hong Kong, June 9-12, 1997.

Dongju Li and Hiroaki Kunieda, ``ASIC Array Processor Design for Regular Algorithm'', Proceedings of RC-TCCAS, Thailand, July, 1996.

Dongju Li, Kazuhito Ito, Hiroaki Kunieda, ``Memory Sharing Processor Array(MSPA) and its Design Methodology'', Proceedings of The Eighth International Conference on Computing and Information, Canada, June, 1996.

Hiroaki Kunieda, Yu-shong Liao, Dongju Li, and Kazuhito Ito,``Automatic Design for Bit-serials MSPA Architecture'', Proceedings of ASP-DAC'95 /CHDL'95 /VLSI'95pp.27-32, Japan, August 1995.

Domestic Research Conference

Dongju Li and Hiroaki, "Programmable Design for Memory Sharing Processor Array (MSPA)'', Technical Report of IEICE of the Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, VLD96-51 (1996-10),pp.09-16, 1996.

Dongju Li, Kazuhito Ito, Hiroaki Kunieda, "ASIC Design Methodology for MSPA Architecture and its application to Data-serial Matrix Multiplier'', IEICE Technical Report on VLD, VLD95-129, ICD95-2 29(1996-03), pp.85-92, 1996.

Oral Presentation

Dongju Li and Hiroaki Kunieda, "Multimedia VLSI based on Window-MSPA Architecture'', Research on Processor Architecture Development Trend for Signal Processing in Next Century(Invited presentation), Tokyo, Nov. 1999.

(dongju@ss.titech.ac.jp),